Explicit calculation for grain boundary barrier height in polysilicon TFTs based on quasi-two-dimensional approach

Abstract

A physical-based explicit calculation to the height of grain boundary barrier has been derived based on the quasi-two-dimensional approach at discrete grain boundaries. The analytical solution is obtained by using the Lambert W function, combining both the uniform distributed deep states and the exponential tail states. The proposed scheme is demonstrated as an accurate and computationally efficient solution in a closed form, which can serve as a basis for the discrete-grain-based models of mobility and drain current in polysilicon thin film transistors. It is verified successfully by comparisons with both numerical simulation and experimental data.