Experimental investigation and manufacturing solution of the rapid thermal process induced overlay residue

Abstract

Experimental investigation for rapid thermal process (RTP) induced overlay residue was conducted. Silicon wafer substrate played a critical part in the RTP induced overlay residue. Substrates with epitaxial layers showed better overlay performance. High device densities tended to show worse overlay residue performance with same RTP process condition. Shallow trench isolation (STI) aspect ratio was one of the major factors that led to severe RTP induced overlay residue. A very minor temperature change at wafer edge during STI liner oxidation could cause significant overlay residue for products with high STI aspect ratio. The experiments revealed that the RTP process chamber temperature controller alone did not exhibit a significant impact to the overlay performance. Better thickness or sheet resistance uniformity did not ensure a better overlay residue performance. In fact, it could be necessary to sacrifice a certain level of thickness or sheet resistance (Rs) uniformity to ensure the following mask process overlay residue within specification. One of the manufacturing solutions was to control the temperature delta of probe seven minus probe six. Another solution was to use a reusable simple short loop wafer to verify the chamber was healthy after major maintenance or critical parts change.