Experimental Demonstration of Non-volatile Capacitive Crossbar Array for In-memory Computing

Abstract

Resistive crossbar arrays for in-memory computing suffer from high static current/power, serious IR drop, and sneak paths. To overcome these challenges, “capacitive” crossbar array that relies on transient current and charge transfer is becoming attractive since it (1) consumes only dynamic power, (2) has no DC sneak paths and avoids severe IR drop along wires, thus is selector-free, (3) can be fabricated on top of the CMOS circuits for potential 3D stacking. In this work, for the first time, we experimentally demonstrated a ferroelectric <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{Hf}_{0.5}\text{Zr}_{0.5}\mathrm{O}_{2}$</tex> (HZO) capacitive crossbar array. The asymmetry of the HZO electrode interfaces leads to the small-signal capacitance on/off ratio>110% that could be read at 0V DC, and a read-disturb-free operation is achieved. The vector-matrix multiplication (VMM) experiments are performed on a fabricated small-scale capacitive crossbar array, showing a linear weighted sum versus either numbers of input or on-state weight. The array-level VMM operation could sustain weight pattern reprogramming after (a) thousands of strong 1ms/3V pulses and (b) an extrapolated 10-year retention at 85°C. Array-level SPICE simulation at 22nm node shows that the energy consumption of a capacitive crossbar array is 20~200x lower than that of a resistive crossbar array counterpart.