Experimental demonstration of inverse-designed silicon integrated photonic power splitters

Abstract

Abstract The on-chip optical power splitter is a common and important device in photonic integrated circuits (PICs). To achieve a low insertion loss and high uniformity while splitting the guided light, multi-mode interferometer-based structures utilizing a self-imaging principle are widely used mainly in the form of a 1 × 2 configuration. Recently, an inverse design method for nanophotonic devices has emerged to overcome the limited capability of the conventional design methods and make it possible to explore the vast number of design parameters. Because of the non-intuitive shape of inverse-designed structures, they allow us to discover interesting and complex optical responses which are almost impossible to find with conventional design methods. Here, we report two kinds of inverse-designed 1 × 4 optical power splitters composed of silicon bars of different lengths, which are fabricated with a standard CMOS-compatible process. The particle swarm optimization method was used to minimize the insertion loss and divide the power evenly into each output port with finite-difference time-domain method simulation. The first optical power splitter has a compact size of 8.14 × 12 μm2 and the second optical power splitter has an even more compact size of 6.0 × 7.2 μm2. With the inverse designed structures, we fabricated the chip with a CMOS-compatible fabrication process. Experimental verification of the structures is provided and good agreement with the numerical results is obtained. The first 1 × 4 optical power splitter has a low insertion loss of less than 0.76 dB and uniformity of less than 0.84 dB, and the second more compact optical power splitter has a low insertion loss of less than 1.08 dB and uniformity of less than 0.81 dB. As the complexity of on-chip photonic systems has steadily increased, the inverse design of photonic structures holds great potential to be an essential part of advanced design tools.