Abstract
Advanced process control in lithography and overall patterning is of tremendous importance for advanced semiconductor Fabs to ensure enhanced chip performance and yield. The final patterning result and subsequent yield are dependent upon many process parameters such as lithography processes, exposure tool performance, etch process, and CMP etc. To control these effects, various knobs, e.g. on the scanner for both wafer inter- and intra-field process control, have been introduced recently, including sophisticated inline metrology. In this holistic lithographic concept, the metrology is supported by simulation and by inline data. Additionally, offline data such as the mask critical dimension uniformity (CDU) data, can be added as a mask wafer interaction, also significantly contributing to wafer intra-field performance. The metrology algorithm now looks for locations where the simulation finds the weakest process features due to strong deviations of focus, dose, stage dynamics or other input parameters. These concepts are optimized to find sites where the process may break. Our concept of “excursion preventions” is a complementary approach. It proactively concentrates on the task to minimize the distributions of critical input parameters as much as possible, independent of a certain pre-defined specification for whether that parameter is met or not. In this paper, we will describe this concept by improving wafer intra-field CDU using CD Correction (CDC) by mask tuning (based on wafer intra-filed data). Mask tuning by the ForTune system uses ultra-short pulse laser technology to change the mask transmission locally, subsequently improving CDU on the wafer (CDC). To ensure safe patterning with a large enough process window without any negative yield or reliability impact, our concept looks for the tail of the final CD distribution instead of traditional 3 sigma numbers. By using a calibrated 3-D resist model, we simulate the pattern result under all permutations of input parameter distributions like dose, focus and mask CDU. As a result of the simulation, we get thousands of CD-results. The tail of that CD distribution still needs to be larger than the minimum CD needed for a safe etch transfer. Secondly, we will show in detail how the pro-active optimization of wafer intra-field CDU by mask tuning using the ForTune CDC process will give us more margin patterning and process stability over any other excursion process (e.g. focus deviations). Furthermore, we will present the simulated yield improvement based on the weak points (hot spots) improvement.
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