Abstract
Implementing high-performance n- and p-type thin-film transistors (TFTs) for monolithic three-dimensional (3D) integrated circuit (IC) and low-DC-power display is crucial. To achieve these goals, a top-gate transistor is preferred to a conventional bottom-gate structure. However, achieving high-performance top-gate p-TFT with good hole field-effect mobility (μFE) and large on-current/off-current (ION/IOFF) is challenging. In this report, coplanar top-gate nanosheet SnO p-TFT with high μFE of 4.4 cm2/Vs, large ION/IOFF of 1.2 × 105, and sharp transistor’s turn-on subthreshold slopes (SS) of 526 mV/decade were achieved simultaneously. Secondary ion mass spectrometry analysis revealed that the excellent device integrity was strongly related to process temperature, because the HfO2/SnO interface and related μFE were degraded by Sn and Hf inter-diffusion at an elevated temperature due to weak Sn–O bond enthalpy. Oxygen content during process is also crucial because the hole-conductive p-type SnO channel is oxidized into oxygen-rich n-type SnO2 to demote the device performance. The hole μFE, ION/IOFF, and SS values obtained in this study are the best-reported data to date for top-gate p-TFT device, thus facilitating the development of monolithic 3D ICs on the backend dielectric of IC chips.
Highlights
“white”-color gate on top of the device is due to the light-reflective Al metal
Of 1.2 × 105, and sharpest subthreshold swing (SS) of 526 mV/decade reported to date at fabrication temperatures of only 100–200 ◦ C. This device has high potential to be integrated into the IMD layer of Si chips for monolithic 3D and brain-mimicking integrated circuit (IC) applications
SS of 526 mV/decade reported to date at fabrication temperatures has the advantage of high hole mobility, it has low bond enthalpy
Summary
Metal-oxide Thin film transistors (TFTs) [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35] have drawn considerable attention due to their high mobility, low fabrication temperature, and simple fabrication process, making them suitable for advanced display [1,2,3,4,5,6] and monolithic three-dimensional (3D) integrated circuit (IC) [15,16,17,18,19,20,21] on amorphous inter-metal-dielectric (IMD) of a Si chip. Because the gate insulator was deposited after the SnO layer, the deposition and post-annealing conditions are crucial to device performance. This is because the p-type SnO is highly sensitive to oxygen partial pressure (Opp ) and annealing temperature, and can be oxidized into oxygen-rich
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