Abstract

The timing properties of asynchronous circuits can be summarized using cyclic graphs that capture max-delay constraints between signal transitions. There are many results on the timing analysis problem, but they all make various simplifying assumptions on the connectivity properties of the underlying timing graph. Most results provide approximate timing characteristics, with a few providing exact results on the circuit’s timing behavior. In this article, we provide results that exactly characterize the timing properties for a more general class of max-delay constraints. We show that the circuit can be partitioned into regions with different periodicities, and provide an efficient algorithm to compute all the periods of the system.

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