Abstract
For verifying the correctness of a circuit, not only its logic function, but also its timing behavior must be considered. Although the path delay fault model can handle part of the weakness of the gate delay fault model, it also has inherent deficiencies. Since the number of paths in a logic circuit is tremendous, exhaustively testing each signal propagation path is prohibitive. To deal with the weakness of traditional delay test techniques, based on the path delay fault model, a new delay test approach including a new delay test output observation method and an adaptive path selection method is proposed in this work. The basic idea of the approach is to measure the signal transition time for each delay test, and more paths are selected for a second-stage test (if necessary) to ensure the timing behavior of the circuit under test. Experimental results obtained by computer simulation demonstrate that a more thorough test is really a need if many significantly late signal transitions are observed.
Published Version
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