Evidence of Transport Degradation in 22 nm FD-SOI Charge Trapping Transistors for Neural Network Applications

Abstract

This article reports on the characterization and analysis of 22 nm FD-SOI CMOS technology-based charge trap transistors (CTT) and their application in neural networks. The working principle of CTT as non-volatile memory depends on trapping and de-trapping of charge in the high-k gate dielectric with the application of voltage pulses on the drain and gate terminals. This programming condition leads to the generation of interfacial traps that can drastically impact device performance. We report degradation in CTT through extractions of subthreshold swing, ON-state current, and mobility. We elucidate transport degradation by correlating effective mobility to interface trap density using a quasi-ballistic transport theory essential for the nanoscale devices under test in this work. Importantly, the trap-induced degradation in CTT transport is not recovered with voltage pulsing at room temperature as our experiments show. We demonstrate the implications of these findings based on analog computation of dot products, an operation of utmost importance to the implementation of artificial neural networks.