Abstract
The International Technology Roadmap for Semiconductors predicts that continued scaling of devices will require ultra-low-k materials with k values less than 2.5 for the 100 nm technology node and beyond. Incorporation of porosity into dense dielectrics is an attractive way to obtain ultra-low-k materials. Electrical and physical properties of ultra-low-k materials have been characterized. Integration evaluations showed both feasibility and challenges of porous ultra-low-k materials. This paper discusses issues and recent progress made with porous ultra-low-k material properties, deposition processes, characterization metrologies, and process integration.
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