Abstract
Hardware in the loop is a widely used technique in power electronics, allowing to test and debug in real time (RT) at a low cost. In this context, field-programmable gate arrays (FPGAs) play an important role due to the high-speed requirements of RT simulations, in which area optimization is also crucial. Both characteristics, area and speed, are affected by the numerical formats (NFs) and their rounding modes. Regarding FPGAs, Xilinx is one of the largest manufacturers in the world, offering Vivado as its main design suite, but it was not until the release of Vivado 2020.2 that support for the IEEE NF libraries of VHDL-2008 was included. This work presents an exhaustive evaluation of the performance of Vivado 2020.2 in terms of area and speed using the native IEEE libraries of VHDL-2008 regarding NF. Results show that even though fixed-point NFs optimize area and speed, if a user prefers the use of floating-point NFs, with this new release, it can be synthesized—which could not be done in previous versions of Vivado. Although support for the native IEEE libraries of VHDL-2008 was included in Vivado 2020.2, it still lacks some issues regarding NF conversion during synthesis while support for simulation is not yet included.
Highlights
The hardware in the loop (HIL) technique has become a very popular approach for power electronics testing in recent years due to its safety and low-cost [1]
The proposed HIL model was simulated in Questa as Vivado has not yet included support for VHDL-2008 with simulation purposes and an external simulator was needed, while for synthesis and implementation, support for the floating- and fixed-point numerical formats (NFs) IEEE
This work presents an exhaustive comparison in terms of MRE, area and speed for a HIL model of a buck converter using the native IEEE libraries for VHDL-2008 in Vivado 2020.2
Summary
The hardware in the loop (HIL) technique has become a very popular approach for power electronics testing in recent years due to its safety and low-cost [1]. The recent inclusion of field-programmable gate arrays (FPGAs) in HIL techniques provoked a significant increase in the field of power electronics. FPGAs are capable of computing a great number of operations in parallel, leading to a low execution time [6,7,8]. This enables the computation of HIL simulations with integration steps of approximately hundreds of nanoseconds [9,10]. The ability to reach such small integration steps results in achieving a better accuracy and enabling the simulation of high-frequency switching converters; reaching this goal is not that easy due to the minimum latency required for the equation’s execution [11]
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