Abstract
Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities such as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them, and test escapes may occur. These undetected faults, associated with weak resistive defects, may affect the FinFET-based SRAM reliability during its lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET-based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed allowing the evaluation of the ionizing particle’s impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFET-based SRAM cell. Results show that weak defects can positively or negatively influence the cell reliability against SEUs caused by ionizing particles.
Highlights
Fin Field-Effect Transistor (FinFET)-based Static RandomAccess Memories (SRAMs) represent one of the current state-of-the-art technologies for integrated systems as theyCommunicated by S
Considering the previsously published work, we propose to analyze the influence of weak resistive defects on the FinFET-based Static Random-Access Memories (SRAMs) robustness under single event effects
The main contributions of this paper are: 1) obtain, by physical simulation, the minimum value of Linear Energy Transfer (LET) of an incident particle that results in a bit-flip ( LETth, or threshold LET) for FinFET SRAM cells designed in a technology equivalent to a 14 nm node; 2) propose a SPICE model for the obtained current curves; 3) investigate the impact of Single Event Upsets (SEUs) on the reliability of FinFET-based SRAMs with weak resistive defects
Summary
Fin Field-Effect Transistor (FinFET)-based Static RandomAccess Memories (SRAMs) represent one of the current state-of-the-art technologies for integrated systems as they. If the affected transistor belongs to a cell’s storage node, this transient current pulse may propagate through the feedback of the cross-coupled inverter, generating a bit-flip [3] Another essential reliability issue in FinFET memory technology is related to weak resistive defects [1] caused by variability in the manufacturing process. The main contributions of this paper are: 1) obtain, by physical simulation, the minimum value of Linear Energy Transfer (LET) of an incident particle that results in a bit-flip ( LETth , or threshold LET) for FinFET SRAM cells designed in a technology equivalent to a 14 nm node; 2) propose a SPICE model for the obtained current curves; 3) investigate the impact of SEUs on the reliability of FinFET-based SRAMs with weak resistive defects. The results obtained in this work may help researchers working on SRAM reliability by providing a feasible simulation flow and important insights of the possible impacts of test escapes, considering non-critical resistive defects, in SRAM field applications susceptible to ion strikes
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