Evaluating the Impact of Temperature on Dynamic Fault Behaviour of FinFET-Based SRAMs with Resistive Defects

Abstract

In recent years, FinFET-based Static Random Access Memories (SRAMs) have become a viable solution to provide the storage of big data volume in Systems-on-Chip (SoCs) as well as to assure high performance deep-scaled devices. As consequence, FinFET-based SRAMs are an extremely viable solution to guarantee the high-performance requirements of deep-scaled devices. However, FinFET-based SRAMs can also be affected by resistive defects that may lead to dynamic faults, which are considered one of the most important causes of manufacturing test escape in deep-submicron technologies. Hence, this paper proposes to evaluate the impact of temperature on the dynamic faulty behaviour of 20 nm FinFET-based SRAM cells affected by weak resistive defects. In more details, the critical resistances and the number of consecutive operations necessary to sensitize faults at the logic level are investigated. Additionally, the concept of Dynamic Behaviour Window (DBW) is defined. Results showed that temperature plays a major part in the sensitization of dynamic faults. Thus, the occurrence of dynamic faults has been mapped combining temperature as well as defect size, and the DBW has been defined considering resistive defects. The proposed evaluation helps to understand the behaviour of dynamic faults in memory cells even better and therefore can be used to improve the test procedures for deep-scaled FinFET memory devices. The proposed analysis has been performed using HSPICE simulations adopting a 20 nm Predictive Technology Model (PTM) of multi-gate transistors based on bulk FinFET.