Evaluation of MTCMOS technique with park mode on chain of 2 input CMOS NAND gate

Abstract

The advances in CMOS technology has contributed largely in scaling down the feature size to achieve high density and performance but this results in an increase in the magnitude of both dynamic and static power dissipation. MTCMOS is most efficient technique for power reduction in CMOS circuits. In this work we evaluated performance parameters of MTCMOS with park mode of operation. For evaluation of MTCMOS with park mode here we consider digital universal logic gate (NAND gate) and the parameters like wakeup time, ground bouncing, and supply bouncing noise, static power dissipation, dynamic power dissipation and delay are considered. All the circuits are simulated using Tanner EDA tool.