A novel high performance low power CMOS NOR gate using Voltage Scaling and MTCMOS technique

Abstract

CMOS logic is extensively used in VLSI circuits but due to scaling of technology, the threshold voltage of the transistors used in CMOS circuits decrease which cause an increase in leakage power. Dynamic power consumption, which is proportional to square of supply voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> further adds to the overall power dissipation. This results in low battery life of mobile devices. In this brief, a novel method to curtail both dynamic power dissipation and leakage power is proposed. The proposed method combines Voltage Scaling and Multi-Threshold CMOS (MTCMOS) technique which helps in reducing dynamic and static power dissipation respectively without degrading the circuit's performance. The proposed technique saves power dissipation by 30% to 90% as compared to conventional CMOS and other existing techniques. A 2-input NOR gate is implemented using the proposed VS-MTCMOS technique in sub-threshold region over different temperatures. Tanner EDA Tool is used to simulate the designed circuit.