Evaluation of HPC Acceleration and Interconnect Technologies for High-Throughput Data Acquisition.

Alessandro Cilardo

doi:10.3390/s21227759

Abstract

Efficient data movement in multi-node systems is a crucial issue at the crossroads of scientific computing, big data, and high-performance computing, impacting demanding data acquisition applications from high-energy physics to astronomy, where dedicated accelerators such as FPGA devices play a key role coupled with high-performance interconnect technologies. Building on the outcome of the RECIPE Horizon 2020 research project, this work evaluates the use of high-bandwidth interconnect standards, namely InfiniBand EDR and HDR, along with remote direct memory access functions for direct exposure of FPGA accelerator memory across a multi-node system. The prototype we present aims at avoiding dedicated network interfaces built in the FPGA accelerator itself, leaving most of the resources for user acceleration and supporting state-of-the-art interconnect technologies. We present the detail of the proposed system and a quantitative evaluation in terms of end-to-end bandwidth as concretely measured with a real-world FPGA-based multi-node HPC workload.

Highlights

Efficient data movement in multi-node systems is a crucial issue at the crossroads of related areas such as scientific data acquisition and computing, big data, and highperformance computing (HPC)
This is strikingly confirmed by a plethora of previous works in the technical literature which point out the key role of high-performance interconnect technologies, e.g., for data acquisition, in demanding applications ranging from high-energy physics [1,2,3] to astronomy [4,5]
Building on the outcome of the RECIPE Horizon 2020 research project, which aimed at the exploration of runtime system management HPC technologies, this work presents a prototype based on state-of-the-art high-performance interconnect technologies, namely InfiniBand EDR and HDR, and remote direct memory access (RDMA) functions for direct exposure of field-programmable gate arrays (FPGAs) accelerator memory

Summary

Introduction

Efficient data movement in multi-node systems is a crucial issue at the crossroads of related areas such as scientific data acquisition and computing, big data, and highperformance computing (HPC) This is strikingly confirmed by a plethora of previous works in the technical literature which point out the key role of high-performance interconnect technologies, e.g., for data acquisition, in demanding applications ranging from high-energy physics [1,2,3] to astronomy [4,5]. Follow the scaling of the interconnect technology, InfiniBand, so that future performance will not be constrained by the custom FPGA implementation of the network interface This communication is structured as follows: Section 2 provides a brief introduction to the relevant technologies and an overview of recent works exploring efficient data movement in the context of accelerator-based big data/scientific computing applications.

Background and Key Technologies

System Architecture

Conclusions