Evaluation of Correlation Power Analysis Resistance and Its Application on Asymmetric Mask Protected Data Encryption Standard Hardware

Abstract

Differential power analyses (DPA) have become great threats to cryptographic chips. However, the DPA resistance evaluation is difficult during circuit design time. In this paper, a simulation test platform at circuit design time and an experimental measurement platform are built to evaluate the DPA resistant capability of cryptographic chips. The design time security evaluation is obtained by dynamic power simulation taking the timing behavior into account, which uses time-based mode PrimeTime Power Extension (PTPX) and accurate timing characterization. The test effects of both platforms are verified on an unprotected Data Encryption Standard (DES) circuit. Then a novel DPA-resistant DES algorithm protected by an asymmetric mask is proposed. Its hardware implementation is realized via field programmable gate array (FPGA). Its power analysis attack resistant capability is evaluated using both simulation and experimental platforms. Compared with non-protected DES, by using five times larger samples and five times longer attack time, the sub-key of the improved DES algorithm still cannot be gained through a correlation DPA attack. Experimental results show the simulation and experimental evaluation platforms are consistent in DPA resistance evaluation, which makes it practical to verify the security at circuit design time. And our proposed asymmetric mask method is effective in protecting the DES algorithm.