Power Aware GALS Based Pipelined DES System

Abstract

The method of cryptography establishes the confidentiality for digital data transmission and storage. Cryptography is used in different applications like ecommerce, health-monitoring and military for protecting information. The Data encryption standard (DES) is widely used cryptographic algorithm due to its symmetric nature and economical implementation to provide short term data security. The same key and architecture set is used for encrypting and decrypting in DES algorithm accordingly. The substitution operation is performed by S-Box by using the key to obtain information uniquely. This paper implements DES algorithm using Globally Asynchronous Locally Synchronous (GALS) methodology which uses independent clock. This improves speed due to its pipelined architecture enabling concurrent data processing. The encryption and decryption engine are implemented by VLSI architecture. This architecture is simulated in Verilog HDL and synthesized on the Xilinx 14.2 device. The logical units of architecture on Field Programmable Gate Array (FPGA) increases by 6.25% to provide improved security. Hence, the speed is improved by trading off with area. This proposed method is proved to be robust for Differential Power Analysis (DPA) which is analyzed from the statistics of the processing time through 50000 encryptions.