Abstract

This paper develops a new algorithm for fault simulation in sequential circuits. Surrogate fault simulation extracts faults from combinational logic and propagates stored faults. Estimates indicate that the one period execution time for all critical steps varies with the first power of the number of gates as opposed to the second power as does a parallel fault simulation.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.