Evaluation and Suppression of a Low-Frequency Output Voltage Ripple of a Single-Stage AC–DC Converter Based on an Output Impedance Model

Abstract

A single-stage ac–dc converter with high power factor (PF) usually suffers from a significant output voltage ripple at double line frequency. In order to suppress such low-frequency output voltage ripple and maintain high PF, a series compensation circuit (SCC), which generates the same magnitude but 180° phase shifted low-frequency voltage ripple, is connected in series with the output of a power factor correction (PFC) converter. In this paper, an output impedance model of the SCC is established and the relationship between the output impedance of the SCC and the low-frequency output voltage ripple of an ac–dc converter is analyzed. Based on the proposed output impedance model, a low-frequency output voltage ripple can be evaluated. To further reduce the low-frequency output voltage ripple, an output impedance shaping method with a virtual impedance is presented. The implementation of the virtual impedance of the SCC with average current mode control is studied. A flyback PFC converter with a buck SCC is implemented for the study of the suppression of the low-frequency output voltage ripple. A prototype is designed to verify the analysis results.