Evaluation and optimization of short channel ferroelectric MOSFET for low power circuit application with BSIM4 and Landau theory

Abstract

Based on BSIM4 parameters of 45nm metal gate/high-k CMOS process and Landau theory, gate and output characteristics of short channel ferroelectric MOSFET (FeFET) are evaluated to explore its optimal structure for low power circuit application. Unlike previously reported simulation results of long channel FeFET, our work reveals that its current–voltage performance is quite susceptible to the parasitic capacitance between the gate and drain. As a consequence, there is a large threshold voltage increase with drain voltage and output characteristics hardly get saturated, indicating that short channel FeFET is not suitable for analog circuit applications. One effective way to address the issues is to minimize the gate-to-drain parasitic overlap and fringing field capacitances. With the tool Purdue Emerging Technology Evaluator, the inverter performance consisting of modified FeFETs is also simulated. Compared with intrinsic inverter, its energy consumption per cycle is much lower at any supply voltage VDD and the propagation delay is also smaller at very low VDD. Our work shows that the optimized FeFET structure, designed by mitigating gate-to-drain parasitic, is suitable for both analog and digital low power circuit designs.