Evaluating regularity extraction in logic synthesis

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Ever decreasing feature sizes coupled with ever increasing scale of integration of modern VLSI systems pose physical and computational challenges for their design, verification and fabrication. For modern VLSI designs, an important component of fabrication cost is the yield loss that an IC experiences. Current high-performance designs are characterized by the presence of numerous bit slices of functionally regular structures that must be preserved during layout generation. This paper proposes a new methodology for regularity extraction at the synthesis level that can be seamlessly integrated into typical top-down ASIC design flow. Our approach identifies the regular logic structures embedded into the high-level circuit description and allows controlling the incurred area penalty. Extraction of these regular structures helps manufacturability during the fabrication process and increases layout predictability. Our work can be directly exploited by regular fabrics to achieve a direct path from a system-level specification and sign-off to the physical implementation.