Abstract

Instruments operating in particle accelerators and colliders are exposed to radiations that are composed of particles of different types and energies. Several of these instruments often embed devices that are not hardened against radiation effects. Thus, there is a strong need for monitoring the levels of radiation inside the mixed-field radiation areas, throughout different positions. Different metrics exist for measuring the radiation damage induced to electronic devices, such as the Total Ionizing Dose (TID), the Displacement Damage (DD) and of course the fluence of particles for estimating the error rates of the electronic devices among other applications. In this paper, we propose an SRAM based monitor, that is used to define the fluence of High Energy Hadrons (HEH) by detecting Single Event Upsets in the memory array. We evaluated the device by testing it inside the H4IRRAD area of CERN, a test area that reproduces the radiation conditions inside the Large Hadron Collider (LHC) tunnel and its shielded areas. By using stability estimation methods and presenting experimental data, we prove that this device is proper to be used for such a purpose.

Highlights

  • The rest of the paper is organized as follows: in section 2 a detailed analysis of the setup, the functionality and the data processing of the monitor is provided

  • While in static mode testing the memory remains in data retention mode and the only source of errors comes from the memory array, i.e. the cells themselves, in dynamic mode testing other sources of upsets may appear

  • In some cases the graphs show that the XS value has fluctuations. This is normal if we take into account that the relative error of the High Energy Hadrons (HEH) fluence calculated for each position is approximately ±40%

Read more

Summary

The monitor configuration

The monitor that we introduce is SRAM based and its functionality relies on the collection and interpretation of the occurring SEUs in the memory array. We propose a monitor that integrates 3 low power commercial 32Mbit SRAMs of 90nm technology As it will be shown later, the overall size of the memory array allows us to collect sufficient data in a small time span. If a Single Event Transient (SET) is induced to the periphery of the memory, it may affect a large number of bit-cells of the memory array This makes more difficult to identify the SEUs that induce Multiple Cell Upsets (MCUs). Even when the monitors operate static mode, besides the period in retention state the memories are read back for retrieving the occurring SEUs. it is possible to observe such phenomena exactly during the time windows needed for the read-back, when the memory is temporarily in dynamic mode. Since the FPGA of the monitor is reconfigurable, the data pattern and the time window between the read-backs of the memory can be modified, according to the needs of each experiment, as well as to calibrate the monitors

Test area
Data processing
Characterization
Results
Conclusions
Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.