Abstract
Integrated circuits sensitive to both total ionizing dose (TID) and displacement damage (DD) effects can exhibit degradation profiles resulting from a combination of degradation mechanisms induced by both effects. This work presents circuit simulations based on experimental data to explain degradation mechanisms induced by combined TID and DD effects on a bipolar IC current source. First, the effect of the degradation of each internal transistor on the circuit's response is evaluated by applying electrical parametric changes. Then simulations are performed from different degradation scenarios based on observed circuit behaviors to reproduce the different TID, DD, and combined TID-DD responses. These simulations show that a synergistic interaction between a current leakage induced by DD on a transistor located in the bandgap reference part with the gain degradation of a current mirror induced by both TID and DD appears to be responsible for the combined TID-DD response. It is also shown that the circuit degradation rate depends on the DDD/TID rate ratios encountered during the exposition.
Highlights
THE total degradation response of integrated circuits exposed to radiation is resulting from the degradation of all their internal transistors [1][2] independently of the technology used (CMOS, BiCMOS, or Bipolar)
The Large Hadron Collider (LHC) environments present a wide range of Displacement Damage Dose (DDD)/Total Ionizing Dose (TID) rate ratios that can lead to completely different degradation rates as it has been demonstrated in our previous work [3] with a bipolar IC current source exposed to different ratios
It has been introduced that integrated circuits sensitive to both TID and Displacement Damage (DD) effects could exhibit combined TID-DD circuit effects when exposed to both effects simultaneously
Summary
THE total degradation response of integrated circuits exposed to radiation is resulting from the degradation of all their internal transistors [1][2] independently of the technology used (CMOS, BiCMOS, or Bipolar). While CMOS technology is only affected by Total Ionizing Dose (TID) and not by Displacement Damage Dose (DDD) (for standard DDD that COTS are exposed to), the bipolar technology, and the BiCMOS one as well, can be affected by both TID, DD, and even Enhanced Low Dose Rate Sensitivity (ELDRS) effect This interaction of the radiation effects at the internal circuitlevel can make challenging the qualification of devices exposed to environments inducing both effects such as the ones present in high energy accelerators, nuclear reactors, or deep space missions. While no qualification standards exist for ICs exhibiting combined TID-DD internal circuit effects, a similar phenomenon has been intensively studied in the literature, which is the qualification of circuits exhibiting circuit effects induced by ELDRS For this effect, it has been shown that for most of the devices the total circuit degradation could be related to the degradation of a single transistor in the circuit such as in [4] and [5].
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