Abstract
Systems Modeling Language (SysML) is the extension and development of Unified Modeling Language (UML) in the field of system engineering. It is gradually applied to the architecture analysis and design of complex hardware and software systems. SysML provides a visual modeling approach in the field of systems engineering that enables a clear explanation of the system's design. However, SysML uses a semi-formal description method [1], which uses natural language to describe the constraints and detailed semantics of systems. This leads to the fact that SysML itself lacks the accurate semantics and it is difficult to conduct rigorous semantic analysis and model quality verification directly. This paper provides a method that transforms SysML state machine into Petri net in propose of overcoming the difficulty of analysis and verification under the dynamic behavior of the state machine. This method also can avoid the formal verification of SysML directly.
Published Version
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