EUV single patterning validation of curvilinear routing

Abstract

Transistor pitch scaling drives the evolution of chip design. The late arrival of EUV lithography prompted the adoption of multiple patterning using 193i to continue transistor scaling. To facilitate multiple patterning integration schemes, the 2D design style was abandoned and unidirectional design style became dominant. As transistor scaling continues further, the demand on routing resources can exceed their supply leading to routing congestion. Exploration on 1.5D or curvilinear routing to resolve higher Metal 2 usage was studied. Nowadays, EUV lithography re-introduced single patterning for the most advanced nodes. At the same time, Multi Beam Mask Writer (MBMW) enables true curvilinear masks. The use of curvilinear routing can potentially resolve routing congestion and more relax design rule check by combining EUV lithography and MBMW. This paper focuses on the challenges in optical proximity correction (OPC) on a design with curvilinear routing. Wafer data will be evaluated to assess quality. The target design is a D-flipflop using 2D and curvilinear features in a local interconnect layer to reduce the congestion. The base pitch of this design was scaled from 40nm to 32nm. The test design was then OPCed using Model Based OPC and Inverse Lithography Technique. Finally wafer data and process window analysis across the pitch range from different OPC variations will be revealed.