Estimation of typical power of synchronous CMOS circuits using a hierarchy of simulators

Abstract

Accurate power-dissipation analysis and correct supply net sizing are crucial aspects of the design of high-quality and low-cost integrated circuits. Information about the typical and maximal currents is required for both the chip and the system design. An accurate method for typical-current estimation is presented. It is based on circuit-level simulation over a number of clock cycles. Traditionally, a fixed large number of clock cycles is simulated. In this method, the number of clock cycles is incrementally calculated depending on the considered circuit and on the specified accuracy. Existing simulators are combined in a hierarchical way: the representation of the node activity during the circuit-level simulation is checked against a high-level simulation over a large number of clock cycles. >