A Booth-like modulo operator

Abstract

In this paper, a Booth-like modulo algorithm is proposed. A hardware architecture that implements the proposed algorithm is also suggested. The proposed algorithm can calculate the modulo of positive and negative numbers in a varying number of clock cycles that is always less than or equal to the number of clock cycles used by traditional techniques such as binary dividers. Hardware simulation results on randomly generated 32-bit data show that the highest average number of clock cycles is less than 14.