Estimation of the influence of irradiation to heavy charged particles on the operation of a MOSFET

Abstract

A technique for evaluating the fault tolerance of an operating semiconductor device to the influence of heavy charged particles (HCP) of galactic origin is considered. The analysis of the influence of ionizing radiation on the electronic device is carried out. The physical processes due to heavy charged particle impact are considered, using well known model of an averaged charge funnel. The carriers generated by the ion track create a current resulting in unwanted effects in external circuits. Single charged particles could be regarded as the microcircuit greatest danger. In order to evaluate the susceptibility of a microcircuit to single events, a rather simple analytical expression for charge collection and a simplified expression for the thickness of the sensitive volume are used. Parameters for two test models (charge carrier density, sensitive volume thickness and charge collection time) are estimated. Calculations have shown, that the local charge carriers density deviation of the order of 1022 cm-3, comparable to the atomic concentration, could be achieved. When an ionizing particle hits the microcircuit, a jump in the current pulse occurs. For an accurate electrical response simulation due to particle propagation the double exponential waveform is used. Charge collection due to drift happens for fractions of a nanosecond, and due to ambipolar diffusion — for nanoseconds The paper presents the results on voltage surges due to HCP impact with the microcircuits. Analysis of chips produced by two different technologies (0.5 /μm and 65 nm) showed higher failure probabilities for an integrated device with the smaller dimensions. As noted earlier, the geometric dimensions of the microcircuit play an important role in the radiation resistance of the system. Also theoretical failure probability predictions are presented for several microcircuits. The proposed approach allows one to give rather quick fault tolerance estimation of a semiconductor device.