ESD protection scheme using CMOS compatible vertical bipolar transistor for 130 nm CMOS generation

Abstract

An ESD protection scheme for 130 nm CMOS LSI is presented. To satisfy both small area requirement for I/O buffer and thin oxide protection capability for power line, we propose an ESD protection scheme using CMOS compatible vertical NPN structure. A vertical bipolar transistor (V-BIP) aided by a trigger diode is adopted for 1.8 V-I/O protection, and realizes high current drive necessary for area efficiency. Another type of V-BIP with optimized low clamp voltage is adopted for power protection, and realizes sufficient protection for sub-2 nm core gate oxide. These devices are fabricated with an addition of one mask for ion implantation to a standard CMOS process. This ESD protection scheme achieves TLP (transmission line pulse) failure current level of 26 mA//spl mu/m, and Human Body Model (HBM) robustness of 50 V//spl mu/m, which is sufficient for 130 nm high performance CMOS LSIs.