A 2.4-GHz Fully Integrated ESD-Protected Low-Noise Amplifier in 130-nm PD SOI CMOS Technology

Abstract

This paper reviews and analyzes a fully integrated ESD-protected low-noise amplifier (LNA) for low-power and narrow-band applications using a cascode inductive source degeneration topology, designed and fabricated in 130 nm CMOS SOI technology. The designed LNA shows 13 dB power gain at 2.4 GHz with a noise figure of 3.6 dB, input return loss of -13 dB for power consumption of 6.5 mW. An on chip "plug-and-play" ESD protection strategy using diodes and power clamp is used at the input and output of the LNA, has an ESD protection level up to 0.8, 0.9 and 1.4-A transmission line pulse (TLP) current. This corresponds to 1.4-kV, 1.2-kV and 2-kV human body model (HBM) stress applied at, respectively, the RF input, RF output and the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> bus. Measurement shows a minor RF performance degradation by adding the protection diodes.