Escape routing design to reduce the number of layers in area array packaging

Abstract

High density multilayer substrate technologies are indispensable to accommodate high input/outputs (I/Os) fine pitch area array integrated circuits (ICs), chip scale packages/ball grid arrays (CSP/BGAs) in the coming packaging generation. They must provide not only a high wiring density, but also an acceptable low cost, short turn around time (TAT) and reliability. Reduction of the number of layers is expected to be a reasonable solution for the conflicting demands. General approaches to reduce the layer count have been to decrease the size of the routing line width and spacing. However, they need changes in the manufacturing processes and materials, causing an increased cost. From escape routing design viewpoint, effects of routing manner on the layer count have been studied. A preferential routing creates specific pad geometry resulting in a high wiring efficiency. This effect can be estimated with an increase in the number of lines per layer routable as a contribution of "the hybrid channel," depending on capture pad pitch-pad diameter-line width-interline space relationship. It is one of the remarkable cases recognized that, within one line per channel rule, the preferential routing can be almost equivalent to that by two lines per channel with regard to the wireability. Its better effect on cost and TAT can also be expected compared with the two thinner sized lines per channel rule, since nothing changes in both manufacturing processes and materials is needed. This method is applicable immediately to packages and boards for assembly of the high I/O flip chips, CSPs, and BGAs.