Error-free algorithm and architecture of radix-10 logarithmic converter

Abstract

The paper presents a fast algorithm to efficiently compute radix-10 logarithm of a decimal number. The algorithm uses a 32-bit floating-point arithmetic, and is based on a digit-by-digit iterative computation that does not require look-up tables, curve fitting, decimal-binary conversion, or division operations; the number of iterations depends on the precision defined by the user. Two numerical examples are shown for the purpose of illustration. The algorithm produces very accurate result with a maximum absolute error of 0.267 × 10 −5 for a 32-bit precision. When implemented on to the Xilinx VirtexII FPGA, the pipelined architecture costs only 2632 logic cells, runs at a maximum frequency of 53.5 MHz, and consumes 117 mW of power. The design is very suitable for timing and accuracy critical applications and compliant with IEEE754-2008 standard.