Abstract
In order to achieve higher system performance, a digital calibration technique for the sub-channel mismatches of time-interleaved ADCs (TIADCs) is proposed in this paper. The sine-fit-based estimation algorithm is introduced to estimate the channel mismatches and a calibration algorithm is proposed to compensate for the mismatches. Subsequently, the genetic algorithm (GA) is firstly utilized to detect the mismatch errors of the outputs of sub-channels after frequency domain filtering. The detected offset error and gain error are then corrected by performing the calibration algorithm, and the time errors are corrected by fractional delay filters based on Farrow structure. The spurious-free dynamic range (SFDR) is enhanced from 19.69 dB to 108.12 dB, and the signal to noise and distortion ratio (SNDR) is enhanced from 16.02 dB to 97.63 dB. The proposed technique is further validated on the FPGA. Compared with existing calibration techniques, the proposed technique has the advantages of simple algorithm structure, low hardware resource consumption, and high calibration accuracy and can be applied to the calibration of high-resolution (18-bit) TIADCs for low-frequency inputs.
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