Erratum: “Controllability of self-aligned four-terminal planar embedded metal double-gate low-temperature polycrystalline-silicon thin-film transistors on a glass substrate”

Abstract

Self-aligned four-terminal n-channel (n-ch) and p-channel (p-ch) planar embedded metal double-gate polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) were fabricated on a glass substrate at a low temperature of 550 °C. This device includes a metal top gate (TG) and a metal bottom gate (BG), which are used as the drive and control gates or vice versa. The BG was embedded in a glass substrate, and a poly-Si channel with large lateral grains was fabricated by continuous-wave laser lateral crystallization. The threshold voltage modulation factors under various control gate voltages (γ = ΔVth/ΔVCG) were nearly equal to the theoretical predictions in both the n- and p-ch TFTs. By exploiting this high controllability, an enhancement depletion (ED) inverter was fabricated, and successful operation at 2.0 V was confirmed.