Abstract
A novel design for a stacked inductor using RLC elements is presented. The proposed model used to predict the stacked inductor is based on a 4-port circuit design with semi-empirical derivation. The modified R S formulas are implemented accurately to predict the series resistance of the stacked inductor. The verification has been carried out using a mature 0.18 mum process to fabricate stacked inductor with various sizes and types. All the measured data are extracted from a silicon device based on a physical layered test system (PLTS). The predicted and measured S-parameter results show excellent correlation in terms of performance for frequencies up to 15 GHz. A high-Q on-chip active inductor is demonstrated using a multiple turns stacked inductor
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