Abstract
A continuous scaling of transistor devices is carried out by not only increasing the drive current but also reducing the off-state leakage current. For short channel devices, the reduction of leakage current is increasingly difficult and hence the use of multi-gate devices is looking increasingly more promising. One of the main areas of concern for multi-gate devices is the higher junction resistance due to high aspect ratio structures in these devices. Hence the use of epitaxy in these junctions is inevitable. In this work, we study the impact of process parameters on the final epitaxial junction shapes and how this affects the junction resistance. It is shown that the epitaxial junctions for n- and p-MOS have different shapes and hence will have to be controlled differently for the most optimum integration scheme.
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