Enhancing error resilience for reliable compression of VLSI test data

Abstract

This paper presents a novel methodology to improve error resilience for reliable compression of test data of VLSI circuits. The presence of so-called (due to the high speed manufacturing test or noise in the Automatic Test Equipment (ATE) head) can lead to a significant loss in coverage when compression is employed. As reported in the technical literature, coverage can experience a reduction of as much as 30% due to bit-flips in the compressed sequence of the test data. Differently from reported works, the proposed technique adds a very small amount of redundant information to test data prior to its compression; the objective of the redundant data is to limit the so-called propagation effect due to bit-flips once the sequence is decompressed. Extensive simulation results are presented to substantiate the increase in error resilience and to evaluate the impact of the redundancy introduced by the proposed approach on the compression ratio. It is shown that for the ISCAS89 benchmark circuits the reduction in coverage is only 0.20%-3.52% which is significantly better than previously reported works.