Evaluation, Analysis, and Enhancement of Error Resilience for Reliable Compression of VLSI Test Data

Abstract

This paper focuses on error-resilience, the capability of a test data stream [which is transferred from an automatic test equipment (ATE) to the device under test (DUT)] to tolerate errors. These errors may occur in an ATE, either in the electronics components of the loadboard or in the high-speed serial communication links. Initially, it is shown that the combined effect of such errors and test data compression can seriously degrade the test quality (as measured by coverage) of the compressed data streams. The effects of errors on compressed streams are analyzed and various test data compression approaches are evaluated. It is shown that for benchmark circuits, the coverage of test sets can be reduced by 10%-30%. Next, two redundancy-based techniques are proposed to improve error-resilience. The objective of the redundant data is to limit the erroneous effect due to bit-flips once the sequence is decompressed. Through extensive simulation, it is substantiated that for the same benchmark circuits and using different compression techniques, the reduction in coverage is only 0.20%-3.52% for a combination of both redundancy techniques. The impact of redundancy techniques on compression ratio is evaluated by experiments and analysis for various test data compression approaches.