Abstract

Introduction In our contribution we report on a fivefold increase of few-layer graphene coverage on a silicon dioxide surface by the introduction of an additional solid carbon source to our silicon CMOS-compatible hydrocarbon CVD process [1]. The extension of our transfer-free graphene has been measured by electrical testing of field effect transistors, using a global silicon back-gate structure and two separated metal catalyst perimeters for source and drain contacts. By this method typical few-layer graphene behavior and full functionality up to a channel length of 10 µm is shown. Additionally, we have analyzed the quality of our extended graphene by means of contact-mode conductive atomic force microscopy. Despite the smooth topography of the graphene several microscopic electrical defects have been found within the few-layer graphene film. The possibility of growing larger area graphene films allows for higher surface active areas, which can be used in sensor applications e.g. humidity sensors [2]. Co integrating graphene to silicon may be advantageous as for the high charge carrier mobility of graphene [3]. Results & Discussion In order to realize the extended growth of transfer-free graphene, conventional p-doped silicon wafers are dry thermally oxidized for the back-gate dielectric. Afterwards, the solid carbon source in terms of a 20nm thick PMMA layer is spin coated onto the oxide, followed by the preparation of a lift-off photoresist for metal patterning. Metal lift-off is then performed using an organic solvent in an ultrasonic bath. During this procedure, the thin PMMA layer is encapsulated below the metal catalyst perimeters (Fig. 1a & b). Subsequently, these substrates are annealed in nitrogen, leading to the decomposition and dissolution of the PMMA into the nickel of the metal catalyst. In the subsequent methane-based catalytic atmospheric pressure CVD process, the nickel is finally supersaturated with carbon, leading to the lateral growth of graphene across the metal catalyst borders onto the silicon dioxide surface (Fig. 2). Electrical testing has been performed in ambient environment using a Keithley SCS 4200 Parameter Analyzer. The devices show a slight p-doping effect, which shifts the Dirac-point to approximately 5V. For the p-type conduction a weak field effect with a current on/off ratio of 3 is observed. Only a negligible change in the subthreshold characteristic is seen with increasing channel lengths, leading to the assumption of a homogenous graphene layer formation. Furthermore, by means of conductive atomic force microscopy the conduction of the surface was measured at a tip bias of 1µV. A continuous conductive surface ensures the presence of a graphene film, whereas no other carbon allotropes appear to be present. [1] P. J. Ginsel, F. Wessely, E. Birinci and U. Schwalke, in Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011 6th International Conference on, p. 1 (2011) [2] A. D. Smith, K. Elgammal, F. Niklaus, A. Delin, A. C. Fischer, S. Vaziri, F. Forsberg, M. Rasander, H. Hugosson, L. Bergqvist, S. Schroder, S. Kataria, M. Ostling and M. C. Lemme, Nanoscale, 7, 19099 (2015) [3] K. S. Novoselov, A. K. Geim, S. V. Morozov, D. Jiang, Y. Zhang, S. V. Dubonos, I. V. Grigorieva and A. A. Firsov, Science, 306, 666 (2004). Figure 1

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