Enhancement of adhesion strength of Cu layer on single and multi-layer dielectric film stack in Cu/low k multi-level interconnects

Abstract

An understanding of adhesion strength at Cu/barrier interface and Cu layer properties at different metal level is necessary to develop a robust planarization (CMP) process without peeling and delamination. This paper quantitatively analyzes the relation between stress and adhesion strength of Cu and its underlying layers of Cu interconnection. The properties of Cu layer on single and dual SiOC dielectric stacks with two different seed layer thickness were systematically studied. Effects of single and dual dielectric stack on stress, adhesion strength and growth orientation of Cu was explored in detail. Strongest adhesion strength between Cu and its underlying layers was found on single dielectric stack of 500 Å Cu seed on Ta barrier. It was reduced significantly after 6 kÅ of Electroplated (ECP) Cu layer was deposited on the stacks of dual dielectric scheme. The adhesion strength/interfacial bonding of dielectrics with Cu was deteriorated by 20% as a result of high stress ECP Cu layer without annealing. In this study, it was found that the properties of conductive Cu layer were strongly influenced by number of dielectric stacks. The results of this study further strengthens our claim that low stress films of dielectric stacks are necessary and essential for enhancing adhesion strength and interfacial bonding between Cu/dielectric layer. Moreover, annealing enhanced the growth of (1 1 1) Cu seed which in turns improved ECP Cu deposition. Better film morphology, improved uniformity of (1 1 1) Cu seed is essential for stress free Cu layer growth.