Enhanced Reliability Scheduling Method for the Data in Register File

Abstract

As technology scales, data reliability in register file has been a subject of extensive investigation, which is highly affected by soft errors caused by single event upset. Thus, the radiation-hardened full-custom and half-custom register file with the ability of detecting and correcting errors are widely used in high reliable processors to mitigate the decrease in reliability. The enhanced data reliability scheduling method for the access of register file is presented in this paper, which is based on the replica of existing data in half-custom register file. In the access of register file, if an uncorrectable error is detected in the data being accessed, the correctness of copy of the existing data being accessed is checked through the roll-back and restart of pipeline and scheduling the access address of source operands. Whether the copy data is free-error or has a correctable error, the right copy data would be used for subsequent operation of processor. Meanwhile if there is an uncorrectable error in copy data, the processor would enter into the exception mode. Finally, the proposed method is evaluated based on IWLS 2005 benchmark program and Poisson reliability model. The results show that the hardware overheads increase only 2%, whereas reliability of data in register file increases 2.5 times at least. This method can significantly improve the reliability of data in register file, which is applied for high reliable RISC processor.