Enhanced Polysilicon Thin‐Film Transistor Performance by Oxide Encapsulation

Abstract

Conventional polycrystalline silicon thin‐film transistor (TFT) fabrication processes rely on an etching process to isolate individual transistors. The subsequent growth of a gate insulator film by thermal oxidation of the islands produces a dielectric film which is significantly thinner along the edges of the island. As a result, the completed transistor exhibits significantly reduced gate breakdown characteristics, as well as other adverse effects related to the higher electric fields along the edges of the transistor channel. This paper discusses an alternative TFT fabrication process which employs a local oxidation process in order to eliminate these adverse effects. Breakdown voltages for 60 nm thick gate insulators on 20 μm long p‐channel TFTs are increased from 37.5 to 60 V. This represents a breakdown field of . Transistors with 5 μm channel lengths, which cannot be reliably fabricated using the conventional process, also exhibit breakdown fields of using this oxide isolation process.