Enhanced Interpolated-DFT for Synchrophasor Estimation in FPGAs: Theory, Implementation, and Validation of a PMU Prototype

Abstract

The literature on the subject of synchrophasor estimation (SE) algorithms has discussed the use of interpolated discrete Fourier transform (IpDFT) as an approach capable to find an optimal tradeoff between SE accuracy, response time, and computational complexity. Within this category of algorithms, this paper proposes three contributions: 1) the formulation of an enhanced-IpDFT (e-IpDFT) algorithm that iteratively compensates the effects of the spectral interference produced by the negative image of the main spectrum tone; 2) the assessment of the influence of the e-IpDFT parameters on the SE accuracy; and 3) the discussion of the deployment of IpDFT- based SE algorithms into field programmable gate arrays, with particular reference to the compensation of the error introduced by the free-running clock of A/D converters with respect to the global positioning system (GPS) time reference. The paper finally presents the experimental validation of the proposed approach where the e-IpDFT performances are compared with those of a classical IpDFT approach and to the accuracy requirements of both P and M-class phasor measurement units defined in the IEEE Std. C37.118-2011. Index Terms— Discrete Fourier transform (DFT), field programmable gate array (FPGA), IEEE Std. C37.118, interpolated discrete Fourier transform (IpDFT), phasor measurement unit (PMU), synchrophasor.