Enhanced Design for Flip Chip Interconnects

Abstract

Multichip and flip chip technology has become increasingly popular in the past years. It employs a series of chips flipped and connected through metallic bumps. A study for improving the performance of flip chip interconnects is recently presented by Ghouz and El-Sharawy for frequencies up to 50 GHz. In that study, the idea of staggering the signal line interconnect with respect to the ground plane bumps to reduce reflection and insertion loss is introduced. In this paper concentration is put on re-shaping the discontinuity region in order to provide a better impedance match between the CPW-motherboard and the CPW-chip, and thus reducing reflection at the input terminals. Several approaches are tested to accomplish lower return loss, among them, the use of bumps of different thickness located at different positions, the use of tilted bumps or "ramps", and the use of dielectric loading on the bumps. The results indicate that the performance of these flip chips is greatly enhanced and extended to frequencies beyond 100 GHz.