Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

Mohamed T Ghoneim,Ernesto B Lizardo,Hossain M Fahad,Aftab M Hussain,Galo A Torres Sevilla,Muhammad M Hussain,Jhonathan P Rojas,Nasir Alfaraj

doi:10.1063/1.4938101

Mohamed T Ghoneim, Ernesto B Lizardo + Show 6 more

Open Access

https://doi.org/10.1063/1.4938101

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Abstract

In today’s digital world, complementary metal oxide semiconductor (CMOS) technology enabled scaling of bulk mono-crystalline silicon (100) based electronics has resulted in their higher performance but with increased dynamic and off-state power consumption. Such trade-off has caused excessive heat generation which eventually drains the charge of battery in portable devices. The traditional solution utilizing off-chip fans and heat sinks used for heat management make the whole system bulky and less mobile. Here we show, an enhanced cooling phenomenon in ultra-thin (&gt;10 μm) mono-crystalline (100) silicon (detached from bulk substrate) by utilizing deterministic pattern of porous network of vertical “through silicon” micro-air channels that offer remarkable heat and weight management for ultra-mobile electronics, in a cost effective way with 20× reduction in substrate weight and a 12% lower maximum temperature at sustained loads. We also show the effectiveness of this event in functional MOS field effect transistors (MOSFETs) with high-κ/metal gate stacks.

Highlights

Ninety percent of today’s electronics are made on low-cost bulk mono-crystalline silicon (100)
Additional accessories are added into the integrated circuits (ICs) using off-chip fans, for providing forced convection, and heat sinks for providing a large surface area for free-convection and heat radiation but, as a trade-off, making the whole system bulky – counterproductive of the idea of ultra-mobility.[5,8,9,10,11,12]
On ultra-thin silicon with deterministic pattern of porous network of vertical micro-air channels, we have demonstrated various functioning physical electronics including MIMCAPs,[41,42] MOSCAPs,[43,44,45,46] MOS field effect transistors (MOSFETs),[47] FinFETs48,49, thermoelectric generators (TEGs),[51] and memristors[52] and have reported their full performance analysis[41,42,43,44,45,46,47,48,49,50,51,52] and their long term mechanical and electrical reliability and stability.[42,43,49,50,53]

Summary

Introduction

Ninety percent of today’s electronics are made on low-cost bulk mono-crystalline silicon (100). Additional accessories are added into the integrated circuits (ICs) using off-chip fans, for providing forced convection, and heat sinks for providing a large surface area for free-convection and heat radiation but, as a trade-off, making the whole system bulky – counterproductive of the idea of ultra-mobility.[5,8,9,10,11,12] Figure 1 highlights the typical arrangement of key IC packaging in a ceramic ball grid array (CBGA) package, with the primary heat flow path starting from the silicon die to the thermal interface material and heat spreader to the heat sink and ambient.[13] Yet, an elusive goal is to have an efficient cooling down process which improves the overall reliability of the devices and circuitry – enhancing the performance.[12,14,15] This is because of the multiple dependencies of semiconductors’ electrical properties on temperature, starting from underlying electronic structure such as the forbidden energy gap (Eg) range[16] up to the actual current (ID) flowing in the devices[17,18,19]; these relations are described by Varshni’s empirical expression

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