English

Abstract

In the designing of any VLSI System, arithmetic circuits play a vital role, subtractor circuit is one among them. In this paper a Power efficient Half- Subtractor has been designed using the PTL technique. Subtractor circuit using this technique consumes less power in comparison to the CMOS and TG techniques. The proposed Half-Subtractor circuit using the PTL technique consists of 6 NMOS and 4 PMOS. The proposed PTL Half-Subtractor is designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. The power estimation and simulation of layout has been done for the proposed PTL half-Subtractor design. Power comparison on BSIM-4 and LEVEL-3 has been performed with respect to the supply voltage on 120nm. Results show that area consumed by the proposed PTL Half-Subtractor is 147.8µm 2 on 120nm technology. At 1V power supply the proposed PTL Half-Subtractor consumes 3.353µW power on BSIM-4 and 3.546µW power on LEVEL-3. The proposed circuit has also been compared with other Subtractor designs using CMOS and TG logics, and the proposed design has been proven power efficient as compared to design by other logics.