Energy-efficient data movement with sparse transition encoding

Abstract

Data movement over long on-chip interconnects is a major contributor to system energy. This paper presents novel signaling and encoding techniques that toget her improve the energy efficiency of data communication between the processor cores and the last level cache. The proposed techniques make the interconnect energy proportional to the number of ones in the transferred data block (i.e., the block's hamming weight), regardless of the previous state of the interconnect. The hamming weight of each cache block is kept low through a sparse data encoding approach to minimize interconnect energy. Simulation results show that the proposed communication scheme reduces the overall L2 cache energy by 30% on a set of eleven parallel applications with a 0.5% average performance degradation.