Dynamic cache memory locking by utilizing multiple miss tables

Abstract

Cache memory plays a vital role in a system's performance by acting as a buffer to quickly supply requested instruction/data blocks from the main memory to the central processing unit (CPU). Cache management techniques may increase or decrease a system's performance. The results vary from process to process, depending on how well optimized the cache management techniques are for a particular process. The inclusion of level-2 (L2) cache locking has been shown in previous studies to be beneficial in increasing a system's performance. This is further improved upon through the inclusion of a miss table (MT), which keeps track of how often each block is missed in the L2 cache. In this research, we propose the use multiple MTs to keep track of the number of times each block is missed in the L2 cache during the run-time of a process. The information obtained from the multiple MTs are then used to lock the most missed blocks into the L2 cache. This is done by dividing the L2 cache into two partitions: a normal partition and a locked partition. Our experiments demonstrate a noticeable performance improvement against the case using only the LRU replacement algorithm.