Abstract
In this paper, we have investigated the effect of a single Grain Boundary (GB) on the performance of decananometre-scale Thin Film Transistors (TFTs) by using the calibrated energy balance transport model and a continuous trap state distribution at the GB. We have found that the GB potential barrier suppresses the subthreshold slope and leakage current in devices, where the DIBL effect and punchthrough currents significantly degrade device performance. We have also found that the drift-diffusion model underestimates the drain current in the single-GB TFT and the velocity overshoot effect becomes significant in the short channel regime. Inclusion of trap-to-band and band-to-band tunnelling models into our simulations have shown that the subthreshold leakage current has a significant field dependence in the negative gate bias regime.
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